Generally, integrated circuits include a complex network of conductive interconnects fabricated on a semiconductor substrate in which semiconductor devices have been formed. Efficient routing of these interconnects requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures.
Within an interconnect structure, conductive vias run perpendicular to the semiconductor substrate and conductive lines run parallel to the semiconductor substrate. According to conventional damascene processing, lines and vias are created within a dielectric layer. A dielectric layer is patterned to create grooves which become lines and holes which become vias. Metal is deposited on the patterned surface such as by electroplating to fill the grooves and holes. Excess is removed, such as by CMP, thereby forming lines along the top of a given dielectric layer, and forming vias which extend below the lines in order to connect to an underlying layer.
Copper or a Cu alloy has recently been preferred to form the conductive interconnects to provide high speed signal transmission between transistors on a complex semiconductor chip. Copper typically requires a barrier layer to prevent it from migrating into, and thereby degrading the insulating capacity of, surrounding dielectric material. As feature sizes continue to decrease in the ongoing development of more and more densely built integrated circuits, the limitations of dielectric damascene and copper are increasingly apparent. For one, smaller feature size of the conductive features generally requires higher aspect ratio, and it is increasingly difficult to fill such features to form void free metal structures. Forming a barrier layer within high aspect features is particularly difficult. Furthermore, as feature sizes continue to decrease, the barrier cannot scale and hence constitutes a greater fraction of any particular feature. Additionally, as the feature dimensions become comparable to the bulk mean free path, the effective resistivity of copper features will increase because of non-negligible electron scattering at the copper-barrier interface and at grain boundaries. See Pawan Kapur et al., Technology and Reliability Constrained Future Copper Interconnects—Part 1 Resistance Modeling, 49: 4, IEEE Transactions on Electron Devices 590 (April 2002).
Some challenges associated with copper damascene can be avoided by forming the interconnect structure by an alternate metal using subtractive metal etch (“SME”), as for example is discussed in co-pending U.S. application Ser. No. 12/885,665 (“Ponoth et al.”) entitled “STRUCTURE FOR NANO-SCALE METALLIZATION AND METHOD FOR FABRICATING SAME” and is hereby incorporated by reference. In SME, a metal layer is deposited, then etched according to one or more patterns to remove all but the interconnect structures. For example, referring to FIG. 1 which represents an integrated circuit according to Ponoth et al., an isolation layer 12 overlies a semiconductor substrate 10, within which at least one semiconductor device has been formed (not shown). A first metal layer may be deposited as a single layer or as a composite of several deposited layers. A first etch to a first depth according to a first pattern defines at least the portion that will become vias 21. A second etch through to isolation layer 12 according to a second pattern leaves wires 20 having depth of the second etch depth and any portions masked by both patterns as vias 21 extending the full height (depth) of the first metal layer. A dielectric layer 25 is deposited over the exposed substrate and the etched first layer metal features. Dielectric layer 25 can be recessed to expose top portions 28 of vias 21. A second interconnect layer of lines 30, vias 31, and dielectric layer 35, can be formed in the same way as the first metal layer. Lines 30 and vias 31 can be aligned with the features of the first metal layer by reference to the location of exposed top portions 28.
A problem with forming multi-layered interconnect structure by subtractive metal etch, however, is that dielectric materials, particularly Si-containing dielectric materials and more particularly porous, low-k dielectric materials, do not adhere well to the patterned metal. Poor adhesion makes the resultant interconnect structure susceptible to failure. Direct deposition of dielectric materials onto such bare metal can produce a structure susceptible to cracking, delamination, or other failure. For example, delamination can occur during fabrication due to stresses from mechanical polishing or from different thermal expansion characteristics of adjacent materials. Poor adhesion can also lead to failure by electromigration.